1. Field of the Invention
The present invention relates to an semiconductor integrated circuit having an improved macro cell pattern.
2. Description of the Related Art
In general, data processing apparatuses need to deal with multifarious pieces of data a bus used for data transmission is coupled with arithmetic units and registers of various bit widths. Particularly, large scale semiconductor integrated circuits (hereinafter referred to as LSI's) often use several internal buses with different bit widths through which data exchange is effected. FIG. 1 is a block diagram illustrating one example of such a data processing apparatus. In FIG. 1, reference numeral 51 denotes an 8-bit data processor comprising an 8-bit arithmetic unit and an 8-bit register, reference numeral 52 an 8-bit data bus, reference numeral 53 a 16-bit data processor comprising a 16-bit arithmetic unit and a 16-bit register, and reference numeral 54 a 16-bit data bus. Here, 8-bit data bus 52 and 16-bit data bus 54 are coupled to a data converter 55 through which data with different bit widths are processed.
Recently, in order to effectively improve the pattern designing of an LSI, the data processor is designed using a data path block. More particularly, the pattern is designed in such a way that a 1-bit data processor has an elongated rectangular shape, and the overall data processor is basically constituted by arranging in parallel such 1-bit patterns (each being called a "leaf" hereinafter) according to the desired bit width of the bus. FIGS. 2A and 2B illustrate examples of a pattern according to the data path method; the former is a plan view of the pattern of a leaf 61 for one bit and the latter illustrates an 8-bit data processor 62 which has eight 1-bit leaves 61 of FIG. 2A arranged in parallel.
When the pattern of an apparatus including data processing apparatuses of various bit widths and buses with various bit widths is designed with the aforementioned data path method, the width of a data path as a macro cell varies depending on the bit width, so that the overall pattern of the data path will not have a rectangular shape. FIG. 3 is a plan view of the general pattern of a data path that has three data processors 71, 72 and 73 combined, which serve as macro cells having 8-bit, 16-bit and 24-bit widths. The hatched regions 74 and 75 in FIG. 3 are wiring regions where aluminum wiring for mutually coupling the data processors is formed. It should be obvious from FIG. 3 that, when the general pattern of the data path becomes complicated, it is likely to cause wastes. For example, providing a connection between other data processors is an example of a complicated data path. It is therefore difficult to provide LSI's with a high integration.
Further, due to the connection of buses or those sections having different bit widths, large wiring regions are necessary, which will hinder high integration of LSI's.